This patent application claims priority based on Japanese patent applications, H11-075494 filed on Mar. 19, 1999 and H11-038673 filed on Feb. 17, 1999, the contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a waveform digitizer using time-interleaved Analog-to-Digital Converters (ADC""s) and it particularly relates to a correcting means which detects and corrects a measurement error accompanied by a phase error of a sampling timing at the time of the time-interleaved AD conversion.
2. Description of the Related Art
In an N-way time-interleaved waveform digitizer using Analog-to-Digital converters (also referred to as ADC""s hereinafter), implementation of a plurality (N) of ADC""s makes possible for an apparent sampling rate to increase. Then, timing of the sampling is required to be precise.
For example, let us consider a 2-way time-interleaved digitizer. Suppose that the number of time series data are 2 to the power of 12, that is 4,096.
First of all, an internal structure for the conventional FFT (Fast Fourier transformation) processing unit will be described. Suppose that there are eight input sampling data, x(0) . . . x(7), where 8 is 2 to the power of 3 (8=23)
Upon receipt of each of 2-way time-interleaved data (4,096 time series data sequences) from an interleaving operation unit 40, the FFT processing unit performs the fast Fourier transformation on the 4,096 time series data, and outputs 4,096 FFT-processed frequency spectrum data. In this case, the internal structure of the FFT processing unit includes the first FFT processing unit, the second FFT processing unit and a butterfly operation unit. The butterfly operation unit plays a role of performing the last steps of the FFT operation. In this instance, the first and second FFT processing units receive respectively 2,048 time series data and perform FFT process on them, and then output the FFT-processed 2,048 time series data (complex-valued data) respectively.
The butterfly operation unit connected to the first and second FFT processing units, outputs 4,096 frequency spectrum data obtained by the butterfly operation (X(0) . . . X(7)).
Here, for the sake of simplicity, suppose that both the first ADC and second ADC have the same identical characteristics such that the timing characteristics at the time of sampling include a group delay characteristic and aperture delay characteristic and so forth.
The analog signals to be measured output from the DUT are supplied to input terminals of both the first ADC and second ADC so that the first ADC takes care of the sampling of even-numbered data sequences, and the even-numbered time series data to be output are labeled D0, D2, D4, . . . The second ADC takes care of the sample of odd-numbered data sequences, and the odd-numbered time series data to be output are labeled D1, D3, D5, . . . Then, upon receipt of both the above data sequences, the interleaving operation unit output the time series data D0, D1, D2, D3, D4, D5, . . . which are alternately interleaved.
In the conventional practice, it was presupposed that sampling timing between a plurality of ADC""s does not fluctuate and that the sampling clock rate is kept constant or the sampling clock rate is constant within an allowable error range. On the other hand, in reality, the sampling characteristics of the ADC""s are affected by irregularity of parts for ADC elements, ambient temperature, deterioration with age and fluctuation of the power voltage and so forth, thereby the sampling intervals which shall be the same fluctuate. Moreover, when utilized in semiconductor testing apparatus which tests and measures the DUT""s with a clock frequency fclk to be sampling-performed being variable in the wide range, the group delay characteristics is changed as the clock frequency fclk changes. Accompanied by all these above factors, there occurs a deviation from an ideal sampling timing. This drawback causes a difficulty in the course of obtaining further accurate frequency spectrum of the input signals.
Therefore, it is an object of the present invention to provide a high-speed waveform digitizer using time-interleaved A-D converters which measures the sampling phase errors and capable of correcting such phase errors in a butterfly operation unit included in an FFT processing unit and a method therefor. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to one aspect of the present invention, there is provided a digitizer for converting an analog signal output from a semiconductor device to a digital signal, comprising: N Analog-to-Digital converters (ADC""s) which sequentially convert the analog signal output from the semiconductor device to the digital signal, a phase error term of sampling time displaced from an ideal timing being denoted xcfx84; an N-way time interleaving unit which interleaves the digital signals output from said ADC""s in sequence and produces data sequence; and a Fourier Trans formation (FT) processing unit for performing FT processing on the data sequence output from said N-way time interleaving unit, the FT processing unit including a butterfly operation unit which inserts a phase error correcting factor to a butterfly operation performed by said butterfly operation unit, so as to correct xcfx84.
In the digitizer, said FT processing unit may perform a Fast Fourier Transformation (FFT) processing on the data sequence or may perform a Discrete Fourier Transformation (DFT) processing on the data sequence.
Moreover, the digitizer may be configured such that an FFT processing unit includes a first FFT processing unit for performing an FFT process in g on an even-numbered data sequence and a second FFT processing unit for performing an FFT processing on an odd-numbered data sequence, and that said butterfly operation unit multiplies the first phase correcting factor of the phase correcting factor to the data sequence which is FFT-processed by said second FFT processing unit.
Moreover, preferably said butterfly operation unit in the digitizer may further multiply the second and third phase error correcting factors of the phase error correcting factors to the data sequence which are FFT-processed by said first and second FFT processing units.
In carrying out the present invention in one preferred mode, the digitizer may be configured that the first phase error correcting factor being denoted xcex1 is represented by
xcex1=exp[jxcfx80xcfx84/Ts]
where Ts is a sampling period of the analog signal and j is a imaginary number unit such that j2=xe2x88x921.
Moreover, the second and third phase error correcting factors being denoted xcex2 and xcex2xe2x80x2, respectively, may be such that xcex2+xcex2xe2x80x2=1.
Preferably, the digitizer having two ADC""s and m=2n input data is configured such that the butterfly operation unit corrects the phase error xcfx84 based on:
X(k)=xcex2{Xeven(k)+xcex1xc2x7{overscore (W)}mkXodd(k)}
X(p)=xcex2xe2x80x2{Xeven(k)+xcex1xc2x7{overscore (W)}mpXodd(k)}
where k runs through 0 and 2nxe2x88x921xe2x88x921, and p runs through 2nxe2x88x921 and 2nxe2x88x921,
xcex2=1/(1+xcex1),
xcex2xe2x80x2=xcex1/(1+xcex1),
{overscore (W)}m=Wm(1+xcfx84/Ts) 
Xeven(k) is an FFT value of an even-numbered data sequence x(even) output from said time interleaving unit,
Xodd(k) is an FFT value of an odd-numbered data sequence x(odd) output from said time interleaving unit, and
X(k) and X(p) are final values output from the butterfly operation unit.
According to another aspect of the present invention, a digitizer having 23(=8) input data and three layered (step) butterfly operation units which correct the phase errors may be provided such that, upon receipt of 8 input data, one (xcfx840) of the total of 8 phase errors (xcfx840, xcfx841, xcfx842, xcfx843, xcfx844, xcfx845, xcfx846, xcfx847) is made as a reference timing and the phase error correcting butterfly operation units correct the phase errors xcfx84""s in a manner that: in the four first-step error correcting butterfly operation units the phase error correcting butterfly operations are performed on (xcfx844xe2x88x92xcfx840), (xcfx846xe2x88x92xcfx842), (xcfx845xe2x88x92xcfx841) and (xcfx847xe2x88x92xcfx843), in the two second-step phase error correcting butterfly operation units the phase error correcting butterfly operations are performed on (xcfx842xe2x88x92xcfx840) and (xcfx843xe2x88x92xcfx841) and in the one third(last)-step phase error correcting butterfly operation units the phase error correcting butterfly operation is performed on (xcfx841xe2x88x92xcfx840).
When there are 4-way time interleaving units for 22(=4) input data, preferably the digitizer having two layered (step) butterfly operation units which correct the phase errors may be provided such that, upon receipt of 4 input data, one (xcfx840) of the total of 4 phase errors (xcfx840, xcfx841, xcfx842, xcfx843) is made as a reference timing and the phase error correcting butterfly operation units corrects the phase errors xcfx84""s in a manner that: in the two first-step error correcting butterfly operation units the phase error correcting butterfly operations are performed on (xcfx842xe2x88x92xcfx840) and (xcfx843xe2x88x92xcfx841) and in a single second(last) -step error correcting butterfly operation unit the phase error correcting butterfly operation is performed on (xcfx841xe2x88x92xcfx840).
According to still another aspect of the present invention, there is provided a method of correcting the phase error of the sampling period of the analog signal output from the semiconductor device, comprising: sequentially converting the analog signal output from the semiconductor device to the digital signal; time-interleaving the digital signals obtained from said converting the analog signal to the digital signal, so as to produce data sequence; and performing Fast Fourier Transformation processing on the data sequence obtained from said time-interleaving, said FFT processing including: inserting at least one phase error correcting factor to a butterfly operation, so as to correct xcfx84.
This summary of the invention does not necessarily describe all necessarily features so that the invention may also be sub-combination of these described features.